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  Datasheet File OCR Text:
 AZ DISPLAYS, INC.
COMPLETE LCD SOLUTIONS
SPECIFICATIONS FOR LIQUID CRYSTAL DISPLAY
PART NUMBER: REVISED:
ACM1002A Series MARCH 14, 2006
General Specification
Item Character Format Module Dimension Viewing Area Dot Size Dot Pitch Character Size Character Pitch Driving View Direction 6H o oDot-Gra phic o Standard Value oCharacter oDigits
Table 1 Unit Dots mm mm mm mm
o ICON with
38.0(W) *25.5(H) *1.8(T) 34.0(W) * 14.0(H) 0.5(W) *0.75(H) 0.55(W) * 0.8(H) 2.7(W) * 5.55(H) 3.2(W) * 6.25(H) 1/18duty, 1/5bias 12H o Other:o oTN, Negative oHTN, Negative oSTN, GrayoSTN, Blue oFSTN, Negative
Polarizer Type
oTN, Positive oHTN, Positive oSTN, Yellow -Green oFSTN, Positive oColor STN oFM LCD
oTransmissive oReflective oTransflective Display Mode oAnti-Glare
Driver IC Interface DC/DC Converter Operation Temperature Storage Temperature
PCF2119_RU/2PHILIPS (c) 6800 o Internal o
2 8080o EAo
External o -20ae-- +70ae -30ae-- +80ae
Page 1
ELECTRICAL CHARACTERISTICS
Absolute Maxium Ratings
No 1 2 3 4 5 6 ITEM OPERATING TEMPERATURE STORAGE TEMPERATURE SUPPLY VOLTAGE FOR LOGIC S U P P LY VOLTAGE FOR LCD INPUT VOLTAGE STATIC ELECTRICITY Symbol T OP T ST VDD VLCD VIN Min. -20 -30 VSS VSS VSS Typ. Max. 70 80 6.5 7.5 VDD +0.5 Unit ae ae V V V
Be sure that you are grounded when handing LCM
Electrical Characteristics
(Ta=25ae VDD =5.0V) Table 4 , No 1 2 3 4 5 Item Supply Voltage For Logic Supply Voltage For LCD Driver Input High Voltage Input Low Voltage Supply Current For Logic Symbol VDD -VSS VDD -Vo (VLCD) VIH VIL IDD Condition / / H level L level / Min. / / 0.7VDD VSS / Typ. 5.0 5.0 / / / Max. / / VDD 0.3VDD 1 Unit V V V V mA
Interface Pin Function
NO 1 2 3 4 5 6 SYMBOL SCL SDA VDD VSS VLCD RESET LEVEL I I Power Supply Power Supply VO I FUNCTION I2C-bus serial clock input I2C-bus serial data input Logic supply voltage. Ground This input is used for the generation of the LCD bias levels. The external reset is active HIGH
Page 2
Timing Characteristics
1. I2C-bus timing diagram.
Timing characteristics: I2C-bus interface: note 2 fSCL SCL clock frequency 400 kHz tLOW SCL clock low period 1.3 ms tHIGH SCL clock high period 0.6 ms tSU;DAT data set-up time 100 ns tHD;DAT data hold time 0 ns tr SCL, SDA rise time notes 1 and 3 15 + 0.1CB 300 ns tf SCL, SDA fall time notes 1 and 3 15 + 0.1CB 300 ns CB capacitive bus line load 400 pF set-up time for a repeated tSU;STA 0.6 ms START condition tHD;STA START condition hold time 0.6 ms tSU;STO set-up time for STO condition 0.6 ms tSW tolerable spike width on bus 50 ns bus free time between STOP tBUF 1.3 ms and START condition Notes 1. Tested on a sample basis. 2. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced toVIL and VIH with an input voltage swing of VSS to VDD . 3. CB = total capacitance of one bus line in pF.
Page 3
Electro-optical Characteristics
No 1 Item Contrast Ratio Rise 2 Response time Down Tf Symbol CR T a=233 ae Tr |E=|E= 12 |E=|E=0 34 130 180 ms Vop=5.0V |E1 |O=270 12H Viewing 3 Angle Range 3H |E3 |O=0 9H |E4 |O=180 4 LCD Driving Voltage VOP T a=233 ae 5.0 V 60 Cr=2 60 |E2 |O=90 T a=233 ae Deg 30 70 1/18Duty 1/5 Bias f=100HZ 160 200 ms Condition Min 4.0 Typ 5.0 Max Unit Drive
6H
Page 4
Commands
The display control instructions control the internal state of the PCF2119_RU/2PHILIPS(c) Instruction is received from MPU to PCF2119_RU/2 PHILIPS for the splay control. The following (c) table shows various instructions. X: Don' care Table 6 t DDDDDDDD RR Instruction BBBBBBBB Description SW 76543210 H = 0 or 1 sets interface Data Length (DL) and D S number of display lines (M); single Function set 00001 0M H L L line/MUX 1 : 9 (SL), extended instruction set control (H) reads the Busy Flag (BF) indicating Read busy flag B internal and address 01 AC F operating is being performed and reads counter address counter contents Read data 11 read data reads data from CGRAM or DDRAM Write data 10 write data writes data from CGRAM or DDRAM H=0 clears entire display and sets DDRAM Clear display 0000000001 address 0 in address counter sets DDRAM address 0 in address counter; also returns shifted display to Return home 0000000010 original position; DDRAM contents remain unchanged I sets cursor move direction and specifies Entry mode set 0 0 0 0 0 0 0 1 / S shift of display; these operations are D performed during data write and read Display control 0 0 0 0 0 0 1 D C B sets entire display on/off (D), cursor
Page 5
on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into the power-down mode Cursor/display shift 0 00001 SR moves cursor and shifts display without //00 changing DDRAM contents CL sets CGRAM address; bit 6 is to be set by the ACG command ` DDRAM address' look at set ; the description of the commands ADD sets DDRAM address
Set CGRAM address Set DDRAM address Reserved Screen configuration Display configuration Icon control Temperature control Set HVgen stages Set VLCD Table7
0
001
0 0 0 0 0 0 0 0
01
H=1 0 0 0 0 0 0 0 0 1 do not use 0 0 0 0 0 0 0 1 L set screen configuration 0 0 0 0 0 0 1 P Q set display configuration II MB T 0000100C 1 S 0010000 1 01V voltage 000001 D M T C 2 S 0 section mode (IM), icon blink (IB), direct mode(DM) set temperature coefficient (TCx) set internal HVgen stages (S1,S0 = 11 not allowed) store VLCD in register VA or VB (V)
Explanations of symbols used in Table 6 BIT I/D S D C B S/C R/L DL H STATE LOGIC 0 decrement display freeze display off cursor off cursor character blink off: character at cursor position does not blink cursor move left shift 4 bits use basic instruction set left/right screen: standard connection (as in PCF2114) 1st 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 1 to 80 r column data: left to right (as in PCF2116); column data is displayed from 1 to 80 row data: top to bottom (as in PCF2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 in single line mode (SL = 1) LOGIC 1 increment display shift display on cursor on cursor character blink on: character at cursor position blinks display shift right shift 8 bits use extended instruction set left/right screen: mirrored connection (as in PCF2116) 1st 16 characters of 32: columns are from 1 to 80 2nd 16 characters of 32: columns are from 80 to 1 column data: right to left; column data is displayed from 80 to 1 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 in single line mode (SL = 1)
L (no impact, if M = 1 or SL = 1)
P
Q
Page 6
row data is displayed from 1 to 8 and icon row data in 17 IM IB DM V M (no impact, if SL = 1) SL C0 character mode; full display icon blink disabled direct mode disabled set VA 1-line by 32 display MUX 1 : 18 (1X32 or 2X?6 1 character display) last control byte; see Table 5
row data is displayed from 8 to 1 and icon row data in 17 icon mode; only icons displayed icon blink enabled direct mode enabled set VB 2-line by 16 display MUX 1 : 9 (1X16 character display) another control byte follows after data/command
Table 8 Explanation of TC1 and TC2 used in Table 6 TC1 TC2 DESCRIPTION 0 0 VLCD temperature coefficient 0 1 0 VLCD temperature coefficient 1 0 1 VLCD temperature coefficient 2 1 1 VLCD temperature coefficient 3; for ranges for TC see Chapter 14 Table 9 Explanation of S1 and S2 used in Table 6 S1 S2 DESCRIPTION 0 0 set internal HVgen stages to 1 (2 * voltage multiplier) 0 1 set internal HVgen stages to 2 (3 * voltage multiplier) 1 0 set internal HVgen stages to 3 (4 * voltage multiplier) 1 1 do not use
Page 7
1/2
AZ Displays, Inc.
ACM1002A SERIES
AZ Displays, Inc.
ACM1002A SERIES
RESET
COM8
ACM1002A SERIES
COM2
E'c
VSS
SEG50
VDD
SEG1 COM10 COM16
SDA SCL
AZ Displays, Inc.


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